ASML, TSMC, and imec have demonstrated a major advance in the effort to bring two-dimensional (2D) semiconductor materials from research laboratories into high-volume semiconductor manufacturing. At the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, the partners unveiled a 300mm wafer integration flow that produced both n-type and p-type 2D-material transistors at a 50nm contacted poly pitch (CPP), marking the first time such scaled devices have been demonstrated using an industry-compatible process.