In the high-stakes theater of global chipmaking, TSMC Chairman C.C. Wei has mastered a rare skill: the art of the well-timed strategic masterstroke.

As advanced packaging technologies continue to evolve toward larger sizes and panel formats, Skytech CEO George Yi stated that in response to the key process requirements of next-generation chip-on-panel-on-substrate (CoPoS) advanced packaging, the company has completed delivery of the world’s first 310mm by 310mm panel-level packaging physical vapor deposition (PLP PVD) equipment. The equipment has been successfully introduced into the production line of a major semiconductor packaging and testing plant in Kaohsiung, Taiwan.

TSMC has formulated a plan to mass-produce advanced 3nm chips in Kumamoto Prefecture, marking an unprecedented move within Japan. The company has notified the Japanese government of this initiative, with estimated equipment investment reaching US$17 billion.